Current Members and HQP

  • Moslem Haidarpor, Post Doctorate Fellow

On FPGA Implementation of Karatsuba Polynomial Multiplier

One of the fast multiplication methods is Karartsuba gorithm. The polynomial edition of extensively studied for efficient realization. These studies try to improve the and cost in both algorithm and device level. However, the question to answer is: does reducing the complexity necessarily results in faster or cheaper hardware?

In this work, we show that this not always the case for the Karatsuba algorithm.

  • Neda Rezaei, Ph.D. candidate

A Negative Voltage Reference for SRAM Units’ Applications

The issue of high-power consumption is an essential design challenge for low power consumer electronics and especially in implementation of the SRAMs. In this work, a novel low power SRAM block is presented, which achieves this goal by reducing the leakage current and power consumption in the SRAM memory design. Reducing the SRAM cells’ leakage current required applying a negative voltage to the NMOS body. As a result, in order to generate a negative DC voltage, this study proposes a negative voltage reference that includes a trimming circuit and a negative level shifter.

  • Hamidreza Esmaeili Taheri, Ph.D. candidate

A New Capacitance to Digital Conversion Technique for CMOS Biosensors

Point-of-care (POC) platforms are getting more and more attraction, owing to their inexpensive, fast, and easy to use nature. An ideal POC platform can take volumes of chemical and biological samples, process them to detect desired target elements, without the need to have professionally trained users . In this research new techniques for capacitance for such sensors are under development.

  • Alex Leigh, Ph.D. student

Hardware Implementation of Spiking Neurons with Reduced Complexity

Digital hardware-efficient approximation of the Izhikevich Spiking Neuron Model has been designed and implemented are under investigation. The result achieved through the development of this neuron is a hardware model that is an approximated version of the above-mentioned model which translates to simple digital circuitry. The efficiencies achieved in the model include a significant reduction in the number of multiplications necessary for modeling spiking phenomena, a reduction of the number of required output bits, and a reduction of the number of input parameters from four to one. All of these efficiencies significantly reduces the model size and cost.

  • Madhan Kumar Thirumoorthi, Ph.D. student

Hardware Security

  • Harikrishnan Balagopal, Ph.D. student

Hardware Security

  • Fadi Edmon, Integrated M.A.Sc. student